I designed a three-op-amp instrumentation amplifier to amplify small differential voltage signals produced by a load cell. The circuit is intended to convert a differential input of 0–20 mV into an approximately 0–3.3 V single-ended signal for a subsequent analog-to-digital converter (ADC).
The objective is to study differential amplification, negative feedback, gain-setting resistors, input impedance, and the influence of common-mode voltage on a practical analog signal-conditioning circuit.
The design uses three operational amplifiers modelled using the Texas Instruments OPA2156 SPICE model. The circuit has been assembled as a schematic and evaluated using KiCad/ngspice. Physical hardware has not yet been built.
Design Specifications
| Application | Load-cell signal conditioning |
| Proposed measurement range | 0–10 kg |
| Target measurement resolution | 1 g (not yet verified) |
| Assumed differential sensor signal | 0–20 mV |
| Target output range | Approximately 0–3.3 V |
| Required nominal gain | 165 V/V |
| Supply voltage | 5 V DC |
| Input common-mode voltage in initial test | 2.5 V |
| Amplifier topology | Three-op-amp instrumentation amplifier |
| Op-amp model | Texas Instruments OPA2156 |
| Simulation software | KiCad/ngspice |
Components Used for Initial Simulation
- Three OPA2156 operational-amplifier SPICE instances
- R1 and R2: 10 kΩ feedback resistors
- R3: 122 Ω first-stage gain-setting resistor
- R4, R5, R6 and R7: 10 kΩ difference-amplifier resistors
- 5 V DC supply source
- Two DC voltage sources representing the differential sensor outputs
- KiCad/ngspice
Schematic Diagram
Circuit Description
The circuit has two functional stages. The first stage uses two non-inverting operational amplifiers with a shared gain-setting resistor. This stage provides high input impedance and amplifies the difference between the two sensor terminals without directly amplifying the full common-mode voltage by the same gain.
The second stage is a four-resistor difference amplifier. It subtracts the two first-stage output voltages to obtain a single-ended output referenced to ground.
Required Gain
For an assumed maximum differential input of 20 mV and a desired output of 3.3 V, the nominal gain is:
G = Vout / Vdiff
G = 3.3 / 0.020 = 165 V/V
This calculation establishes the total differential gain required from the signal-conditioning circuit. The actual sensor sensitivity, excitation conditions and ADC input requirements must be confirmed during system integration.
First Stage – Gain Setting
The first stage uses two amplifiers with equal feedback resistors R1 and R2. The gain-setting resistor R3 connects the two inverting-input junctions.
For equal feedback resistors R1 = R2 = R, the ideal differential gain of this stage is:
G1 = 1 + (2R / R3)
Using R1 = R2 = 10 kΩ and R3 = 122 Ω:
G1 = 1 + (2 × 10000 / 122)
G1 ≈ 164.93 V/V
The selected values closely match the nominal gain target. The 122 Ω resistor determines the differential gain together with the two 10 kΩ feedback resistors; it is not a resistor to ground.
Analysis of the First-Stage Voltages
For the initial full-scale DC operating-point test, the two input voltages were set to:
V1 = 2.510 V V2 = 2.490 V
Vdiff = 2.510 − 2.490 = 0.020 V
With stable negative feedback, the inverting-input voltages are approximately equal to their respective non-inverting inputs. Therefore the voltage across R3 is approximately 20 mV.
IR3 = (2.510 − 2.490) / 122
IR3 ≈ 163.93 µA
Because the op-amp inputs draw very little current, Kirchhoff's Current Law requires approximately the same current to flow in the external feedback resistors. The current is provided and absorbed by the op-amp output stages through the resistor network; it does not originate from an op-amp input pin.
The approximate voltage magnitude developed across each 10 kΩ feedback resistor is:
VR = 163.93 µA × 10000 ≈ 1.6393 V
For the upper amplifier, current in the feedback branch causes the output to settle above its 2.510 V input node:
Vupper = 2.510 + 1.6393 ≈ 4.149 V
For the lower amplifier, current flows from its inverting junction toward the amplifier output through the feedback resistor. Its output therefore settles below 2.490 V:
Vlower = 2.490 − 1.6393 ≈ 0.851 V
The resulting first-stage differential output is:
Vupper − Vlower ≈ 3.299 V
These calculations explain why one amplifier produces approximately 4.15 V while the other produces approximately 0.851 V, even though the original sensor terminals differ by only 20 mV.
Second Stage – Difference Amplifier
The second stage uses four resistors: R4, R5, R6 and R7. R4 connects the lower first-stage output to the inverting input, while R5 connects the final output back to that inverting-input junction. R6 connects the upper first-stage output to the non-inverting input, and R7 connects that non-inverting junction to ground.
The resistor pairs were selected with equal nominal values:
R4 = R5 = R6 = R7 = 10 kΩ
The R6–R7 pair forms a voltage divider. With equal resistance values and negligible op-amp input current:
V+ = Vupper × R7 / (R6 + R7)
V+ ≈ 4.149 / 2 ≈ 2.075 V
Negative feedback through R5 causes the inverting-input junction to settle at approximately the same voltage:
V− ≈ V+ ≈ 2.075 V
Purpose of the Input and Feedback Resistors
The lower first-stage signal is approximately 0.851 V, but the third amplifier's inverting junction is approximately 2.075 V. R4 allows those two points to be at different voltages while establishing a defined current between them.
IR4 = (2.075 − 0.851) / 10000
IR4 ≈ 122.4 µA
Since negligible current enters the inverting input, approximately 122.4 µA must arrive at that junction through feedback resistor R5. The output must therefore be higher than the junction by:
VR5 = 122.4 µA × 10000 = 1.224 V
Vout ≈ 2.075 + 1.224 = 3.299 V
R4 establishes an input current from the lower amplifier, and R5 provides negative feedback that determines the output voltage needed to balance that current. Directly connecting the 0.851 V signal to the inverting junction would not produce the same subtraction behaviour.
More generally, applying Kirchhoff's Current Law at the inverting-input junction gives:
(Vout − V−) / R5 = (V− − Vlower) / R4
When R5 = R4, this becomes:
Vout = 2V− − Vlower
Because R6 = R7, V− is approximately Vupper / 2. Therefore:
Vout = Vupper − Vlower
The four equal resistor values make the second stage a unity-gain difference amplifier. It is the matching of the resistance ratios, rather than the specific choice of 10 kΩ, that determines the ideal subtraction behaviour. In hardware, resistor-ratio errors can reduce common-mode rejection and introduce measurement errors.
Initial SPICE Simulation
The circuit was simulated in KiCad/ngspice using the OPA2156 manufacturer SPICE model, with a 5 V supply, a 2.510 V upper input and a 2.490 V lower input.
| Measurement | Ideal calculation | Simulated result |
|---|---|---|
| Upper first-stage output | 4.149 V | 4.15 V |
| Lower first-stage output | 0.851 V | 0.851 V |
| Final single-ended output | 3.299 V | 3.28 V |
The simulated final output differed from the ideal value by approximately:
(3.299 − 3.28) / 3.299 × 100 ≈ 0.6%
The initial DC simulation therefore supports the predicted differential gain at this operating point. The difference between the ideal calculation and simulation has not yet been separated into individual model effects or other sources of error.
SPICE Model Integration and Convergence
The OPA2156 manufacturer model represents one amplifier, whereas the original KiCad OPA2156 dual-package symbols use multiple schematic units. For simulation, individual five-terminal op-amp symbols were assigned to the manufacturer's model and connected to the existing three-amplifier circuit.
The model pin assignments included non-inverting input, inverting input, positive supply, negative supply and output. Each amplifier was supplied from 5 V and ground.
Initial operating-point runs failed to converge and reported singular-matrix and timestep errors. After checking model assignments, the complete circuit subsequently produced a successful operating-point result. The precise reason for the earlier convergence failures was not established, so this remains a simulation issue to investigate if it recurs.
Results
For a 20 mV differential input centred on 2.5 V, the first-stage amplifier outputs were approximately 4.15 V and 0.851 V. The final difference amplifier produced approximately 3.28 V, close to the ideal 3.299 V prediction.
The results confirm the intended operation at one full-scale DC input condition. They do not, by themselves, confirm linearity across the complete signal range, accuracy at low input levels, common-mode rejection, input-referred noise or 1 g measurement resolution.
Further Development
The next simulation steps are to sweep the differential input from 0 to 20 mV, measure output linearity, and investigate input offset, noise, resistor tolerances, common-mode rejection and temperature-dependent errors.
The 1 g target corresponds to an assumed differential signal increment of approximately 2 µV per gram and an ideal output increment of approximately 0.33 mV per gram. Whether that resolution is achievable depends on the complete sensor, amplifier and ADC noise and error budget, which is not yet characterised.
A physical implementation will also require a verified load-cell specification, practical power-supply decoupling, suitable resistor tolerances, an ADC interface and an appropriate treatment of unused amplifiers in dual-op-amp packages. Laboratory measurements will then be compared with the analytical and SPICE results.
Datasheet: Texas Instruments OPA2156
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